Address Read Write 0 00 Encoder 0 low byte Assembly Register low byte 1 01 Encoder 0 mid byte Assembly Register mid byte 2 02 Encoder 0 hi byte Assembly Register hi byte 3 03 Encoder 1 low byte 4 04 Encoder 1 mid byte Timer config Register 5 05 Encoder 1 hi byte 6 06 Encoder 2 low byte 7 07 Encoder 2 mid byte 8 08 Encoder 2 hi byte 9 09 Encoder 3 low byte 10 0A Encoder 3 mid byte 11 0B Encoder 3 hi byte 12 0C Index Sense Register Encoder Control Register 13 0D Digital Inputs 0-7 14 0E Digital Inputs 8-14,Estop 15 0F Module ID code 0x41 value to DAC via P8 16 10 Assembly register low byte 17 11 Assembly Register mid byte 18 12 Assembly Register hi byte, set Axis 0 rate 19 13 Assembly register low byte 20 14 Assembly Register mid byte 21 15 Assembly Register hi byte, set Axis 1 rate 22 16 Assembly register low byte 23 17 Assembly Register mid byte 24 18 Assembly Register hi byte, set Axis 2 rate 25 19 Assembly register low byte 26 1A Assembly Register mid byte 27 1B Assembly Register hi byte, set Axis 3 rate 28 1C Rate Generator Control Register 29 1D Load Setup Time Register 30 1E Load Step Pulse Width Register 31 1F set/clear Estop, SSR outputsThe encoder read registers are a 24-bit straight binary up/down counter broken into three bytes. The MSB contains a normal, 2's complement sign. This value represents the count of edges of the quadrature waveform coming in the A and B inputs to the board from the encoders. This 24-bit value has been latched into a holding register, so there will be no mis-reading of the value due to encoder counts being received during the read of the three bytes.
Encoder Control Register Bits : Bit # 7 6 5 4 3 2 1 0 Axis # 3 2 1 0 3 2 1 0 Function ---Load Position--- ---Index Select----The load position bits will cause that axis's encoder counter to load the 24-bit value now in the assembly register. This bit needs to be set to a one, held for at least 2 uS, and then cleared back to zero. Multiple axes can be set at the same time, if setting all to the same value.
The Index select bit, when 1, will cause that axis's 24-bit latch to only latch the encoder count when the index pulse is sensed from the encoder. It will latch on the rising edge of the index pulse. This will also set the index sense bit in the index sense register. If the Index Select bit is 0, then the latch will latch the count every time the Intr bus signal is asserted. This will happen when the timer generates a pulse or when it is commanded by soft latch bit in the timer register.
Timer Register Bits :
Bit # 7 6 5 4 3 2 1 0
Function none none soft master tim3 tim2 tim1 tim0
latch
Description of Timer Register Bits :
Index Sense Register Bits : Bit # 7 6 5 4 3 2 1 0 Axis # 3 2 1 0The 4 LS bits are a latch for sensing of the index pulse. The axis must have the index select bit turned on in the control register, and this register must be read once (which clears it after the read) before the values are meaningful.
Step Rate Generator : The step rate generator operates from a 10 MHz clock, and divides this by the count in a 24-bit register. A 24-bit counter starts at zero, and counts up until the specified count is reached. It then is reset to zero, and starts again. A step pulse is issued at that time. This scheme is used so that when the computer requests a rapid increase in step rate, the response will not have to wait for one last pulse at the old rate. The comparator is a magnitude comparator, not an equality comparator, so that any count that exceeds the divisor immediately causes a step. This divisor works like this: 0 is illegal, 1 will cause a step rate of 5 MHz, 2 will cause a step rate of 3.333 MHz, 4 will cause a rate of 2.5 MHz, etc. A divisor of (2 ^ 24) -1 will cause a step rate of approximately 0.5 Hz.
The Assembly Register is a 24-bit register that assembles a 24-bit value from 3 bytes input to the board. When the 3 bytes have been assembled, they are loaded into one of the counters through the control register. These registers are arranged so that all 12 can be written to in a burst, after setting the address of the first one with the IEEE-1284 nADDRSTB signal. The Rate Generator Control Register follows the address of the last axis rate register, so it can be written, also, without sending the address.
Rate Generator Control Register : Bit # 7 6 5 4 3 2 1 0 Axis # 3 3 2 2 1 1 0 0 function run dir run dir run dir run dirThe run bit causes that axis to begin generating step pulses at the programmed rate. The dir bit sets the direction of that axis to 1 or zero, as set by the dir bit. The change in the direction output may be delayed due to the setup time selected.
The step pulse and direction signal have circuitry to control the relationship of these signals, to match the needs of various stepper drivers. The setup time register holds a value, from 0 to 254, representing times from .1 to 25.4 uS, that changes in the direction bit will be delayed by, after a step pulse, or that the step pulse will be delayed by when the direction changes. (Don't put 255 in this register.) The value can be calculated like this : value = 255-(time in us)*10 Note that the 'Mariss' switch on the DIP-switch gives another method of selecting the relationship of direction signal timing to the step pulse. See the switch settings for more info on this.
The step pulse width register holds a value, from 0 to 254, representing time from .1 to 25.4 uS for the width of the step pulse. (Don't put 255 in this register.) Calculate the value like this : value = 255-(time in us)*10
Addressing the module : This board accepts an address on the 5 LS bits of the data bus during assertion of ADDRSTB on the EPP bus to select which register will be read or written. The 4 MS bits are used to select which board is addressed. The convention, at present, is to have the first universal stepper board at address 000xxxxx, and the 2nd board, if any, at 001xxxxx. After each data byte is transferred, the internal address counter increments. You can select the first address in the board (first addr in first board would be 00000000 ) and then read all 12 bytes (3 bytes x 4 axes) with 12 consecutive read data operations, causing the DATASTB line to pulse.