Address Read Write 0 00 Encoder 0 low byte Assembly Register low byte 1 01 Encoder 0 mid byte Assembly Register mid byte 2 02 Encoder 0 hi byte Assembly Register hi byte 3 03 Encoder 1 low byte Encoder Control Register 4 04 Encoder 1 mid byte Timer config Register 5 05 Encoder 1 hi byte 6 06 Encoder 2 low byte 7 07 Encoder 2 mid byte 8 08 Encoder 2 hi byte 9 09 Encoder 3 low byte 10 0A Encoder 3 mid byte 11 0B Encoder 3 hi byte 12 0C Index Sense Register 13 0D Digital Inputs 0-7 Index Preset Register 14 0E Digital Inputs 8-14,Estop 15 0F Module ID code 0x52 value to DAC via P8 16 10 Axis 0 Timestamp Low* Assembly register low byte 17 11 Axis 0 Timestamp High* Assembly Register hi byte, set Axis 0 Duty Cycle 18 12 Axis 1 Timestamp Low* Assembly register low byte 19 13 Axis 1 Timestamp High* Assembly Register hi byte, set Axis 1 Duty Cycle 20 14 Axis 2 Timestamp Low* Assembly register low byte 21 15 Axis 2 Timestamp High* Assembly Register hi byte, set Axis 2 Duty Cycle 22 16 Axis 3 Timestamp Low* Assembly register low byte 23 17 Axis 3 Timestamp High* Assembly Register hi byte, set Axis 3 Duty Cycle 24 18 Timestamp Counter Low* 25 19 Timestamp Counter High* 26 1A 27 1B 28 1C PWM Generator Control Register 29 1D Load PWM Frequency Register (lo byte) 30 1E Load PWM Frequency Register (hi byte) 31 1F set/clear Estop, SSR outputs * NOTE: Timestamp registers only present in post-2007 firmware
Encoder Control Register Bits : Bit # 7 6 5 4 3 2 1 0 Axis # 3 2 1 0 3 2 1 0 Function ---Load Position--- ----- Unused -----The load position bits will cause that axis's encoder counter to load the 24-bit value now in the assembly register. This bit needs to be set to a one, held for at least 2 uS, and then cleared back to zero. Multiple axes can be set at the same time, if setting all to the same value.
Index Preset Register Bits : Bit # 7 6 5 4 3 2 1 0 Axis # 3 2 1 0 Function --- none --- ---Index Preset----The index preset bit, when set to 1, will cause that axis' 24-bit position counter to be loaded with the value contained in the encoder preset register whenever a rising edge on the encoder's index (Z) signal is detected.
Timer Register Bits : Bit # 7 6 5 4 3 2 1 0 Function none none soft master tim3 tim2 tim1 tim0 latchDescription of Timer Register Bits :
Index Sense Register Bits : Bit # 7 6 5 4 3 2 1 0 Axis # 3 2 1 0The 4 LS bits are a latch for sensing of the index pulse. The axis must have the index select bit turned on in the control register, and this register must be read once (which clears it after the read) before the values are meaningful.
PWM Generator : The PWM generator operates from a 10 MHz clock, and divides this by the count in a 16-bit register. (On the UPC Rev 3.1 and later, the clock is 40 MHz, rather than 10. The ID register of this board will report 0x53 or a higher digit in the 4 least significant bits) for the 40 MHz units.) A 16-bit counter starts at the value in the 16-bit PWM Frequency Register, and counts up until all bits are one. It then is reset to the value in the PWM frequency register, and starts again. At this time, if the PWM control register enable bit is a one, the PWM output goes to a logic one. While the counter is counting up, the count value is compared to the value loaded into the PWM duty cycle register. When the counter's value is greater than the value in the PWM duty cycle register, the output drops to zero.
The Assembly Register is a 24-bit register that assembles 16- and 24-bit value from 2 or 3 bytes input to the board. When the bytes have been assembled, they are automatically loaded into the multi-byte destination register. This prevents each byte from being loaded as the computer sends it, which could cause a mixture of old and new bytes to be combined. These registers are arranged so that all 8 PWM bytes can be written to in a burst, after setting the address of the first one with the IEEE-1284 nADDRSTB signal.
PWM Generator Control Register : Bit # 7 6 5 4 3 2 1 0 Axis # 3 3 2 2 1 1 0 0 function run dir run dir run dir run dirThe run bit enables that axis to generate PWM pulses at the programmed rate and duty cycle. The dir bit sets the direction of that axis to 1 or zero, as set by the dir bit.
Addressing the module : This board accepts an address on the 5 LS bits of the data bus during assertion of ADDRSTB on the EPP bus to select which register will be read or written. The 3 MS bits are used to select which board is addressed. The convention, at present, is to have the first universal PWM board at address 000xxxxx, and the 2nd board, if any, at 001xxxxx. Dip Switch position 10 should be ON for the first board and OFF for the second. After each data byte is transferred, the internal address counter increments. You can select the first address in the board (first addr in first board would be 00000000 ) and then read all 12 bytes of the encoder position (3 bytes x 4 axes) with 12 consecutive read byte operations, causing the DATASTB line to pulse.