Pico Systems

Quadrature Encoder Counter Register Definition

Address       Read                       Write
 0         Axis 0 low byte           Assembly Register low byte
 1         Axis 0 mid byte           Assembly Register mid byte
 2         Axis 0 hi  byte           Assembly Register hi  byte
 3         Axis 1 low byte           Control Register
 4         Axis 1 mid byte           Timer config Register
 5         Axis 1 hi  byte           Encoder Filter Rate Select
 6         Axis 2 low byte
 7         Axis 2 mid byte
 8         Axis 2 hi  byte
 9         Axis 3 low byte
10         Axis 3 mid byte
11         Axis 3 hi  byte
12         Index Sense Register
13         not used                  Index Preset Reg
14         not used
15         Module ID code 0x14
   *** Following register only on 5/27/2013 firmware and later
           (This rev ID's as 0x14)
16         Axis 0 Timestamp Low
17         Axis 0 Timestamp High
18         Axis 1 Timestamp Low
19         Axis 1 Timestamp High
20         Axis 2 Timestamp Low
21         Axis 2 Timestamp High
22         Axis 3 Timestamp Low
23         Axis 3 Timestamp High
24         Timestamp Counter Low
25         Timestamp Counter High

The axis read registers are a 24-bit straight binary up/down counter broken into three bytes. The MSB contains a normal, 2's complement sign. This value represents the count of edges of the quadrature waveform coming in the A and B inputs to the board from the encoders. This 24-bit value has been latched into a holding register, so there will be no mis-reading of the value due to encoder counts being received during the read of the three bytes.

The Holding Register is a 24-bit register that assembles a 24-bit value from 3 bytes input to the board. When the 3 bytes have been assembled, they can be loaded into one of the counters through the control register.

Control Register Bits :
  Bit #   7     6     5     4     3     2     1     0
  Axis #  3     2     1     0     3     2     1     0
Function  ---Load Position---     ----- Unused  -----

The load position bits will cause that axis's encoder counter to load the 24-bit value now in the assembly register. This bit needs to be set to a one, and then cleared back to zero.

Timer Register Bits :
  Bit #   7     6     5     4     3     2     1     0
Function none  none soft  master tim3  tim2  tim1  tim0
                    latch

Description of Timer Register Bits :

SoftLatch - when there is no 'master' encoder, then writing a 1 to this bit generates a software controlled latching of the encoder counts. Write a 0 after writing the 1.
Master - Setting this bit to 1 selects this encoder counter as the master board, such that it drives the bus Intr line to cause any other encoder counters to also latch the count, and any DAC16 boards to update the analog value from the holding registers. Leaving this bit at 0 (power on default) causes the board to accept the Intr signal from other units.
TIM(3:0) These select the count down divisor from a 10 KHz clock. 1111 means don't divide, so the encoder will be latched every 100 uS (10 KHz). The counter counts up to 1111 from whatever value is entered, so a setting of 0110 (6) will go through 10 states before automatically reloading this value. Therefore, loading 6 here will make the encoders latch at a 1 KHz rate.

Index Preset Register

Index Preset Register Bits :
  Bit #   7     6     5     4     3     2     1     0
  Axis #                          3     2     1     0
Function  ---    none     ---     ---Index Preset----

The index preset bit, when set to 1, will cause that axis' 24-bit position counter to be loaded with the value contained in the encoder preset register whenever the encoder's index (Z) signal is detected. This bit must be held as a 1 until the encoder clock has ocurred (maximum time 1 us).

Index Sense Register Bits :
  Bit #   7     6     5     4     3     2     1     0
  Axis #                          3     2     1     0

The 4 LS bits are a latch for sensing of the index pulse. The axis must have the index select bit turned on in the control register, and this register must be read once (which clears it after the read) before the values are meaningful.

Encoder Filter Rate Select

Encoder Filter Rate SelectBits :
  Bit #   7     6     5     4     3     2     1     0
  Axis #  3     2     1     0     3     2     1     0
Function  ----------- unused ------------   rate select
                  1    MHz                    0     0
                  2.5  MHz                    0     1
                  5    MHz                    1     0
                  10   MHz                    1     1

The Encoder digital filter can be set to 4 rates, 1, 2.5, 5 and 10 MHz. This will suppress any invalid state transitions shorter than the inverse of that rate.

Timestamp Register

The Timestamp feature is only present on boards with the 5/27/2013 or later firmware, identified by a module ID code of 0x14 or higher. The timestamp system has a master 16-bit counter incrementing at 1 MHz. Whenever a count is registered by an encoder, the current timestamp count is latched by the encoder counter. When the encoder count is read out, the timestamp counters can also be read out. These are unsigned 16-bit values, with the most significant bits in the higher-numbered address. Also, the last two registers of this group are the raw counter value, so a time between last encoder count and when the encoder counts were latched can be determined. All the timestamp values are latched at the same time the encoder counts are latched (under control of timer register).

Board Addressing

This board accepts an address on the 4 LS bits of the data bus during assertion of ADDRSTB on the EPP bus to select which register will be read or written. The 4 MS bits are used to select which board is addressed. The convention, at present, is to have the first encoder counter at address 0000xxxx, and the 2nd board, if any, at 0001xxxx.

The DIP switch at SW1 sets the board address. Switch 4 is the most significant position, switch 1 is the least significant. On sets the bit to 0, off sets it to 1. For an address of 2 (which would cover a range of EPP addresses 20-2f (or 20-3f on the boards with 2/27/2013 or later firmware) you would set DIP switch 2 off, all others on.

NOTE: On boards with 5/27/2013 and later firmware, odd board addresses are not possible, as each board occupies two address units. So, DIP switch position 1 is not used, and addresses would be 0,2,4, etc.

After each data byte is transferred, the internal address counter increments. You can select the first address in the board (first addr in first board would be 00000000 ) and then read all 12 bytes (3 bytes x 4 axes) with 12 consecutive read data operations, causing the DATASTB line to pulse.

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